/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2024 Napatech A/S
 */

#ifndef _NTHW_FPGA_REG_DEFS_STA_
#define _NTHW_FPGA_REG_DEFS_STA_

/* STA */
#define STA_BYTE (0xa08364d4UL)
#define STA_BYTE_CNT (0x3119e6bcUL)
#define STA_CFG (0xcecaf9f4UL)
#define STA_CFG_CNT_CLEAR (0xc325e12eUL)
#define STA_CFG_CNT_FRZ (0x8c27a596UL)
#define STA_CFG_DMA_ENA (0x940dbacUL)
#define STA_CFG_TX_DISABLE (0x30f43250UL)
#define STA_CV_ERR (0x7db7db5dUL)
#define STA_CV_ERR_CNT (0x2c02fbbeUL)
#define STA_FCS_ERR (0xa0de1647UL)
#define STA_FCS_ERR_CNT (0xc68c37d1UL)
#define STA_HOST_ADR_LSB (0xde569336UL)
#define STA_HOST_ADR_LSB_LSB (0xb6f2f94bUL)
#define STA_HOST_ADR_MSB (0xdf94f901UL)
#define STA_HOST_ADR_MSB_MSB (0x114798c8UL)
#define STA_LOAD_BIN (0x2e842591UL)
#define STA_LOAD_BIN_BIN (0x1a2b942eUL)
#define STA_LOAD_BPS_RX_0 (0xbf8f4595UL)
#define STA_LOAD_BPS_RX_0_BPS (0x41647781UL)
#define STA_LOAD_BPS_RX_1 (0xc8887503UL)
#define STA_LOAD_BPS_RX_1_BPS (0x7c045e31UL)
#define STA_LOAD_BPS_TX_0 (0x9ae41a49UL)
#define STA_LOAD_BPS_TX_0_BPS (0x870b7e06UL)
#define STA_LOAD_BPS_TX_1 (0xede32adfUL)
#define STA_LOAD_BPS_TX_1_BPS (0xba6b57b6UL)
#define STA_LOAD_PPS_RX_0 (0x811173c3UL)
#define STA_LOAD_PPS_RX_0_PPS (0xbee573fcUL)
#define STA_LOAD_PPS_RX_1 (0xf6164355UL)
#define STA_LOAD_PPS_RX_1_PPS (0x83855a4cUL)
#define STA_LOAD_PPS_TX_0 (0xa47a2c1fUL)
#define STA_LOAD_PPS_TX_0_PPS (0x788a7a7bUL)
#define STA_LOAD_PPS_TX_1 (0xd37d1c89UL)
#define STA_LOAD_PPS_TX_1_PPS (0x45ea53cbUL)
#define STA_PCKT (0xecc8f30aUL)
#define STA_PCKT_CNT (0x63291d16UL)
#define STA_STATUS (0x91c5c51cUL)
#define STA_STATUS_STAT_TOGGLE_MISSED (0xf7242b11UL)

#endif	/* _NTHW_FPGA_REG_DEFS_STA_ */
